When I run the design through PrimeTime and Timing Analyzer, why do more paths appear in PrimeTime?
The Verbose Report of Minimum Paths indicates that race/hold analysis is no longer performed for MAXDELAY FROM:TO constraints. Because of this, the hold will not be checked for multicycle paths (slow or fast exception) and might be another potential area of discrepancy between TRCE/PrimeTime, as PrimeTime does check hold for this case.
This is definitely a discrepancy issue; however, two things should be noted: first, it is still possible to cover a multicycle path with a PERIOD constraint and perform a race/hold check; second, it is highly unlikely that a slow exception path will have a race/hold violation, as these paths usually require a longer amount of time to reach their destination.
Fast exceptions can be potential issues when comparing PrimeTime to TRCE. To obtain a fast exception to analyze, use one of the following suggestions:
- Xilinx recommends that TRCE users create FROM:TO constraints for the fast exceptions. If you want to perform a hold/race check on this path, create a PERIOD constraint instead of a FROM:TO constraint.
- Translate the resultant group constraints to SDC.
- Leave the MAX delays as FROM:TO constraints in translation to SDC and PrimeTime.