We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 17708

9.1i PrimeTime - How should the Timing Analyzer clock uncertainty from the timing report correlate to PrimeTime?


How is the "clock uncertainty" in the Xilinx Timing tools converted into the SDC?


Set the "set_clock_uncertainty" in the translation for IOB Paths.

This issue is addressed in the latest "xp_clock_latency.tcl" script from Synopsys.

AR# 17708
Date 01/18/2010
Status Archive
Type General Article
Page Bookmarked