General Description: What changed between the 1.78 and 1.81 versions of the speed files for Virtex-II Pro? Where can I access these files for 5.2x?
What did not change in the Virtex-II Pro Speed Files version 1.81?
The production speed files for 2VP7, speed grade -5 remains unchanged. The production speed files for 2VP20, speed grade -5 remains unchanged.
Key Changes in Virtex-II Pro Speed Files Version 1.81
The following devices and speed grades are designated as production:
2VP30, 2VP40, 2VP50, and 2VP70 are now PRODUCTION for speed grade -5.
2VP7, 2VP20, 2VP30, 2VP40, 2VP50, and 2VP70 are now PRODUCTION for speed grade -6.
The remainder of the speed grade designators remain unchanged from the previous (version 1.78) release of the speed files. Compared to the previous release of the speed files, version 1.78, the following resources are slower:
An error occurs in a model used in the Horizontal Longs just above and below the PPC (RC_PPC_HLONG). In these two rows, the correct value shows the HLL a bit slower (250-420ps).
The following resources are now faster: - Global clock. - Vertical long lines. - Tsrck and Tceck are faster in -7 and -6.
Additional Adjustments: Input delay line values were placeholders and have been adjusted so that they line up with the silicon.
This model for measuring IOB output delays does not consider the effects of external board loading on the Xilinx device clock-to-out times. For this reason, it is necessary to perform an IBIS model simulation to generate accurate clock-to-out times.
5.2x History: Historically, the specification for the loading on the pins was 35pF, but because Xilinx supports so many different standards, each with its own specification, the loading on the test equipment was different for different standards.
Xilinx then made all specifications uniform at 35pF load. Essentially, this changed the specification for many of the I/O standards, some of which were 0pF, while others were 10pF, and so on. This change caused many adjustments to change radically because relative to the baseline of the clock-to-out (Tiockp), some standards were much worse. However, devices with a stronger driver were able to handle the extra load more easily and looked better by comparison at 35pF.
Shortly after these changes were released, Xilinx decided that (based on the quick transition ability of today's circuits) a transmission line model with 0pFd and 50 Ohm loading was more appropriate. It is important to note that none of these speed files changes occurred because of a change in silicon performance.
The Virtex-II Pro speed files are also based on a 0pFd and 50 Ohm loading since the 5.1i software.