We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 17736

Virtex2Pro Configuration - Configuration with third-party tools, DONE pin does not go High unless the TCK frequency is significantly reduced


General Description:

When programming a JTAG chain with Virtex-II Pro using third-party Boundary Scan tools, the DONE pin does not go High unless TCK frequency is significantly reduced to as low as 250 KHz. Other than the normal 33 MHz Boundary Scan limitation, is there a limitation for the TCK frequency when a Virtex-II Pro is in the chain?


NO. However, if an external pull-up on the Virtex-II Pro TDO is not used, then the TCK frequency must be reduced. The reason for this is because TDO in a Virtex-II Pro is an open drain driver and not an active driver. As a result, TDO only drives Low. To go High, TDO is released internally and needs to be pulled High externally with a pull-up resistor. If another device is in the chain after the Virtex-II Pro and an external pull-up is not used, then the TDI pin on the second device can pull this signal High because TDI has a weak internal pull-up. However, the rise time is so slow that JTAG will work only when the TCK period is relatively long.

To run at faster TCK frequencies, you must add an external pull-up resistor on TDO. The value of the external pull-up resistor depends on the capacitive loading on the TDO pin and the operating frequency. Xilinx recommends that you use a resistor of 200 Ohms or higher. You can determine the optimal TDO pull-up value with IBIS simulation.

AR# 17736
Date 12/15/2012
Status Active
Type General Article