A design with an internally generated clock routed through a global buffer via the BUFG=CLK attribute will function properly in simulation but not on the device.
When a clock is routed to a global buffer via the BUFG=CLK attribute, the clock is output to a Global Clock pin and read back into the device on the same pin. As a result, this pin will toggle and you must ensure that the pin is not held at a known level on the board.
A software bug prevents the Global Clock input buffer from being configured properly and causes the registers clocked by this internally generated clock to not toggle. This bug affects only the CoolRunner-II family.
This problem has been fixed in the latest 6.1i Service Pack, available at:
The first service pack containing the fix is 6.1i Service Pack 1.