UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 1793

VERILOG-XL: Error! acc_replace_delays() [PLI-NOAPPREPMIPD] Error modifying MIPD: no XL loads on port

Description

Keywords: Verilog-XL,

Urgency: Standard

Problem Description:
When using the Cadence's PLI routines to back-annotate a post layout file
with Verilog-XL, the following error messages are generated:

Error! acc_replace_delays() [PLI-NOAPPREPMIPD]
Error modifying MIPD: no XL loads on port
PR8.PLL.AGS
"PR8.spec", 10: $tdc("PR8.option");

Error! acc_replace_delays() [PLI-NOAPPREPMIPD]
Error modifying MIPD: non-XL loads on port
PR8.PLL.BP
"PR8.spec", 10: $tdc("PR8.option");

Error! acc_replace_delays() [PLI-NOAPPREPMIPD]
Error modifying MIPD: non-XL loads on port
PR8.PLL.FN
"PR8.spec", 10: $tdc("PR8.option");

Error! acc_replace_delays() [PLI-NOAPPREPMIPD]
Error modifying MIPD: no XL loads on port
PR8.PLL.DYB
"PR8.spec", 10: $tdc("PR8.option");

Solution

The meaning of the error message "no XL loads on port PR8.PLL.AGS" and
"no XL loads on port PR8.PLL.DYB" is that the ports AGS and DYB are
floating. This violates a rule of SDF back annotation that the ports that are
back-annotated must have to be connected to accelerable entities in Verilog-XL.

In a similar manner, the port cannot be connected to a non-accelerated pin,
unless through an acceleratable buffer.

This is usually seen when using the Turbo algorithm which accelerates
the simulation of behavioral constructs.
AR# 1793
Date Created 08/31/2007
Last Updated 08/26/2003
Status Archive
Type ??????