I have a testbench that I wrote for functional simulation that have generics in them. When I try to reuse this testbench in my Timing simulation, the simulator errors out about the entity in testbench not matching the gate-level net list.
Is there a way to work around this?
There is a way to work around this without having to write a new testbench for the post-Place and Route simulation netlist.
Using the -a switch with NetGen will generate an architecture only back-annotated HDL file.
In doing so, the entity of the RTL definition that contains the generic can be re-used and, as long as the top-level ports are defined as std_logic_vector, it should be able to bind the entity to the gate-level netlist.
Example netgen command:
netgen -sim -a <infile> [<outfile>]