General Description: When I attempt to execute the "View HDL Instantiation Template" process for a DCM component, the process fails and reports an error similar to the following:
"Compiling source file "dcm2.v" vhdtdtfi:Declaration (Module dcm2) not found. tdtfi (verilog) completed with errors. ERROR: vhdtdtfi failed Process "View Verilog Instantiation Template" did not complete.
Done: failed with exit code: 0001."
This problem may occur if a Single DCM component is created with Project -> New Source -> IP (COREGen and Architecture Wizard) and the file name (Verilog) is written with uppercase letters. The module argument is being incorrectly set to lowercase characters.