We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 17971

6.1i ISE - The "View HDL Instantiation Template" process fails for a DCM component, reporting "vhdtdtfi:Declaration (Module <dcm_name>) not found."


Keywords: View HDL instantiation template, vhdtdtfi, compiling, source, DCM, case, Project Navigator, Verilog

Urgency: Standard

General Description:
When I attempt to execute the "View HDL Instantiation Template" process for a DCM component, the process fails and reports an error similar to the following:

"Compiling source file "dcm2.v"
vhdtdtfi:Declaration (Module dcm2) not found.
tdtfi (verilog) completed with errors.
ERROR: vhdtdtfi failed
Process "View Verilog Instantiation Template" did not complete.

Done: failed with exit code: 0001."


This problem may occur if a Single DCM component is created with Project -> New Source -> IP (COREGen and Architecture Wizard) and the file name (Verilog) is written with uppercase letters. The module argument is being incorrectly set to lowercase characters.

This problem has been fixed in the latest 6.1i Service Pack, available at:
The first service pack containing the fix is 6.1i Service Pack 1.
AR# 17971
Date 02/07/2006
Status Archive
Type General Article
Page Bookmarked