General Description: The following problem occurs sporadically when a 1G MAC core is configured in CORE Generator to implement the statistics logic using block RAM:
While transmitting and receiving IDLE frames, the statistics counters count up when they should also be idle. As a result, the values stored in the counters (number of bad frames, frame length, etc.) are incorrect.
The statistics logic uses a shift register to reset the updates for the statistics data. This register is clocked by RX_CLK. If the RX_CLK input clock to the shift register becomes unstable, this can cause the shift register to contain invalid data, which results in erroneous statistics.
A patch for v3.0 of the GMAC core fixes this issue by inserting a clock recovery circuit in front of the shift register. To resolve this issue, please install the patch, which is available in the Release Notes: (Xilinx Answer 17129).