The FPGA Compiler command set_wire_load "parttype-s_wc" causes the following error:
Wire load not found "parttype-s_wc"
This is caused by the link and target libraries in the .synopsys_dc.setup file not being set to the part that is being targeted. The example setup file fc4k.synopsys_dc.setup in $ds401/examples/synopsys looks like:
target_library = {xprim_4005-5.db xprim_4000-5.db xgen_4000.db \ xio_4000-5.db xfpga_4000-5.db}
If the xprim_4005-5 is missing, or the wire load is being set for a different part, you will receive this error.
Set the xprim_####-#.db in the link and target libs in the setup file to the correct part and speed grade. Make sure that the link and target are identical.
AR# 1800 | |
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Date | 02/25/2014 |
Status | Archive |
Type | General Article |