Does MXE support mixed language VHDL and Verilog simulations?
No, MXE does not support mixed language simulations. You can simulate either VHDL or Verilog, but not both at the same time.
However, you can simulate a mixed language design after implementation, as back-end simulation netlist will be created using either Verilog or VHDL, but not both. As long as the testbench is generated using a single language, the simulation netlist can be created using the same language, allowing MXE to be used for the simulation. In 6.1i, you can select the language which will be used to create the simulation netlist by right-clicking the device in the source window, selecting Properties, and changing the Generated Simulation Language to either VHDL or Verilog.