The input setup/hold requirement reported by TRCE seems excessive for my design. Is the value correct?
The example below shows a Virtex-II Pro Tiopick parameter that is in accordance with the data sheet specification. However, the pin-to-pin setup/hold specifications are not yet available in the data sheet.
The TRCE report snippets below show the "constraint section" (Figure 1) and the "data sheet pin-to-pin setup/hold section" (Figure 2). The design is a system-synchronous, single data rate (SDR) design that uses the CLK0 output of the DCM to capture data in a 2VP7-5. The pin-to-pin setup and hold section shows a ~ 1.8 ns setup/hold window. Is this correct?
The Virtex-II Pro data sheet specifications are available in the "DC and Switching Characteristics" section of the data sheet at:
Single data rate (SDR) and double data rate (DDR) designs that do not use local clock inversion have global pin-to-pin setup values that are over-reported by the timing analysis (TRACE) tools. These types of designs will require a hand calculation to achieve the correct setup times and slack in the design. Please see the "Prorating Information" and "Hand Calculation" sections below.
The hand calculation will be required until 6.1i Service Pack 2, which will be available in mid-October, 2003.
Virtex-II Pro pin-to-pin setup and hold times are characterized with a DDR circuit design utilizing local clock inversion in the IOB. (Refer to Figure 3 below or to (Xilinx XAPP259), System Interface Timing Parameters, Figure 7.)
- In the case of SDR designs with a single clock, no local inversion of the clock is required.
- In the case of DDR designs, much of the duty cycle distortion (DCD) uncertainty associated with local inversion clocking designs may be removed from the setup/hold window by using an additional global clock and the CLK180 (or by using CLK90 with CLK270) output of the DCM. The following circuit diagram illustrates this method:
TRCE does not distinguish between the two circuits presented (Figure 3 and Figure 4). Consequently, the pin-to-pin setup/hold values reported by TRCE in the data sheet section of the timing report are unnecessarily large for the following types of designs:
- DDR designs using two global clocks (CLK0/CLK180 or CLK90/CLK270 outputs)
- SDR designs using a single clock
For these designs, a simple hand calculation using a characterized prorating value can be performed to determine the correct pin-to-pin setup/hold and slack values reported by the timing analysis tools.
The pin-to-pin setup/hold values for Virtex-II Pro devices have been re-characterized using a complementary global clock circuit. The following tables show the prorating values (Tprorate) across the Virtex-II Pro device family for a DCM setting in source-synchronous mode and system-synchronous mode:
NOTE: You can set the system-synchronous or source-synchronous mode using the DCM attribute "DESKEW_ADJUST".
Refer to the following documents for more information on setting the DESKEW_ADJUST attribute:
- The Xilinx Application Note "System Interface Timing Parameters" (Xilinx XAPP259).
- "Virtex-II Pro and Virtex-II Pro X FPGA User Guide" at: http://www.xilinx.com/support/documentation/user_guides/ug012.pdf
Go to the Digital Clock Manager (DCMs) section under Design Considerations.
Denoting the setup time reported in TRCE from any particular pin as "Tsetup", the slack as "Tslack", and "Tprorate" in the prorating tables, the equations for determining the correct setup and slack times are:
Tcorrect_slack = Tslack + Tprorate
Tcorrect_setup = Tsetup - Tprorate
The TRCE report snippets previously described show the constraint section and the data sheet pin-to-pin setup and hold values. Using the same design, the calculation is as follows:
For the input signal SSRAM_DQ:
Correct Slack for SSRAM_DQ = 0.458 + 0.421 = 0.879 ns
Correct Setup for SSRAM_DQ = 2.042 - 0.421 = 1.621 ns
Please note that the hold times do not change.