All versions of the Xilinx SPI-4.2 core have pinout requirements for SPI-4.2 bus signals. All RDat, RDClk, RCtl, TDat, TDClk, TCtl, and SysClk signals are constrained via UCF files to specific bank and I/O locations. If these constraints are altered, the core will be invalidated, and performance and functionality will not be guaranteed.
Users should place Status signals and Status clocks based on design requirements. If possible, place RStat and RSClk in the same bank as the RDat data bus, and place TStat and TSClk in same bank as the TDat data bus.
Please review the supported device table available in the SPI-4.2 data sheet. The pinouts are compatible across device families within the same package, speed, and configuration. For example, 2VP20, 2VP30, 2VP40, and 2VP50 devices all have unique UCF files, but the pinout constraints are the same within the same package (e.g., FF1152), same speed (e.g., -5), and same configuration (e.g., static).
Xilinx strongly recommends that you use the available configuration listed in the table.
If you need a specific device, package, or configuration that has not been released, contact your local FAE or Xilinx Customer Support.