UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 1810

M1.3 MAP: BLKNM, HBLKNM, RLOC and LOC Properties May Not be Respected by MAP in Some Instances

Description

Keywords: map blknm hblknm rloc loc

Urgency: hot

General Description:

Architecture(s): XC4000E/L/EX/XL, XC5200/L

Reference Numbers: 12904, 12934

MAP first maps logic based on FMAP/HMAP combinations before it
tries to follow any user-specified BLKNM, HBLKNM, RLOC or LOC
properties. MAP may therefore ignore user-specified properties
like BLKNM, HBLKNM, RLOC or LOW.

When the properties are ignored, MAP will issue a warning
similar to the following:

<OUTPUT>
WARNING - Unable to combine AND2 symbol and BUF symbol
</OUTPUT>

Solution

1

2

Workarounds are design-specific:

If MAP is combining two LUTs (lookup tables, which includes
FMAPs and HMAPs) into the same CLB, for example, one with
BLKNM=fred, and the other with no BLKNM, and this is not what
you want, you can prevent the combination by attaching a
different BLKNM to the LUT that you do not want combined with
the BLKNM=fred logic.

You should also attach X attributes to the nets that you want
mapped as the external outputs of the logic you are trying
to map into the CLB in question.

You may also try creating the desired configuration in EPIC,
and converting it into a physical macro. This may then
be instantiated into your design. For more information on
creating physical macros, refer to the online (Xilinx Manual
EPIC Design Editor Reference/User Guide)

If all else fails, you may have to manually remove the
properties and allow MAP to operate without them.
AR# 1810
Date Created 01/30/1997
Last Updated 04/03/2000
Status Archive
Type General Article