UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 1816

CPLD XC9500 Family - How do I determine low-power mode timing (tLP, tLOGILP)?

Description

General Description:

How to I determine the path timing of an XC9500 macrocell in low power mode?

Solution

When determining path timing in low power mode, use tLOGILP in place of tLOGI.

For example, the following path in low power mode would be calculated as:

tPD = tIN + tLOGILP + tPDI + tOUT

9500 Timing Model
9500 Timing Model

The Xilinx Application Note "Using the XC9500XL Timing Model" (Xilinx XAPP111) discusses timing calculations in detail.

AR# 1816
Date Created 08/21/2007
Last Updated 12/15/2012
Status Active
Type General Article