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CPLD XC9500 Family - How do I determine low-power mode timing (tLP, tLOGILP)?
How to I determine the path timing of an XC9500 macrocell in low power mode?
When determining path timing in low power mode, use tLOGILP in place of tLOGI.
For example, the following path in low power mode would be calculated as:
tPD = tIN + tLOGILP + tPDI + tOUT
9500 Timing Model
The Xilinx Application Note "Using the XC9500XL Timing Model" (Xilinx XAPP111) discusses timing calculations in detail.
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