AR# 18188

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7.1i XST - "ERROR:Xst:1539 - <VHDL file name> line xx: Formal port in component <comp> must be an identifier"

Description


General Description:

XST fails with the following error message:



"ERROR:Xst:1539 - myfile.vhd line 39: Formal port in component <mycomp> must be an identifier."

Solution


This error occurs if a component is instantiated with a type conversion on the ports as in the following example.



Example



signed(c) => c;



To work around this issue, follow these steps:

1. Insert a signal:

signal c_std : std_logic_vector(7 downto 0);

2. Change the line:

signed(c) => c;

to:

c => c_std;

3. Add this line after the port map:

c <= signed(c_std);



This error occurs when synthesizing VHDL code generated from ECS schematics with a lower-level schematic containing only one output vector (no inputs). This type of component is typically created to generate a constant value.



Example

The following code is from an ECS schematic with a component internally tied to ground symbols to create the constant 0000.



instgnd : gnd4

port map (G(3 downto 0)=>constants(3 downto 0));



To fix this problem, create symbol components with multiple pins. To create constant expressions to use within a schematic, refer to (Xilinx Answer 16526).
AR# 18188
Date 02/15/2012
Status Archive
Type General Article
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