General Description: When doing a VHDL flow (ECS schematics or straight VHDL source) through XST where generics are used, you might run into the following HDLParser error:
"ERROR:HDLParsers:3324 - top_level.vhd Line 22. IN mode Formal d of ff with no default value must be associated with an actual value."
followed by another error:
"ERROR:HDLParsers:164 - H:/applications/xst/open_ports/top_level.vhd Line 24. parse error, unexpected PORT."
What is causing these problems?
When doing an instantiation of a component that has a generic:
u1 : ff generic map (test => "abc"); port map (d => d, r => '1', c => c, q => q);
placing a semi-colon after the generic map indicates to the compiler that the instantiation has completed. In this case, the component declaration included ports, so the compiler returns an error stating that (in this case) port 'd' is not associated with a signal.
The resolution is to remove the semi-colon after the generic map.
If you are doing a schematic flow then you have encountered a known bug with the ECS tool. The only known work-around for the present is to: 1. Open the ".vhf" file that ECS created. 2. Remove the semi-colon after the generic map. 3. Save the ".vhf" file as a ".vhd" file. 4. Remove the schematic from the design and replace it with the newly saved ".vhd" file.