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AR# 18236

8.1i CORE Generator - "Error: User has selected the Foundation ISE Flow. Current project is not a valid ISE project."


Keywords: Project, ISE, bus notation, synthesis, flow, options

When attempting to generate a core, I received the following error messages:

"ERROR: User has selected the Foundation ISE Flow. Current project is not a valid ISE project. ISE symbol file has not been generated.
ERROR: Did not generate ISE symbol file for core <core_name>."


CORE Generator looks for the existence of an ISE project before allowing a symbol to be created when the COREGen Flow Vendor is set to ISE.

If you want to create IP Cores outside an ISE project directory but still assure that the netlist bus format is set correctly for integration with XST, do the following:

1. Open CORE Generator project options by selecting Project -> Project Options.
2. Under Output Options, select Flow Vendor, VHDL or Verilog, and Other.
3. Make sure the Netlist Bus Format is set to B<n:m>
4. Click OK to close the Project Options window, then generate the desired core(s).

NOTE: In order to automatically create symbol files for ECS schematic capture, cores must be created in an ISE project directory.
AR# 18236
Date 12/12/2006
Status Archive
Type General Article
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