During configuration of a Virtex-II device, a given output might transition from Low to High prior to the DONE pin being released. The output stays High until DONE has been released, at which time the output then goes to the initial state defined for that output by the design. The transition High is caused by a pull-up becoming enabled; the I/O does not actually drive High.
In Serial and SelectMAP configuration modes, the output might transition High in the tens of milliseconds before DONE is released. In JTAG, if this is the first configuration after power-up, the behavior is the same as mentioned above. However, if the device is being reconfigured, the output might transition High immediately upon reconfiguration (DONE transitioning Low) and stay High until reconfiguration is complete.
This behavior has been observed with LVTTL and LVCMOS33 I/O standards, and likely occurs with other I/O standards as well.
This behavior is not observed when Hot Swapping is enabled (HSWAPEN_B pin is pulled low) because in this case all the I/Os on the device are pulled High throughout configuration.
In addition to the output transitioning during configuration, the output might also be seen to glitch immediately upon pulsing the PROG pin Low. See (Xilinx Answer 18278) for more details.
Xilinx strongly recommends designing systems in such a way that outputs from the device are ignored during configuration. If the system cannot ignore transitions on outputs during configuration, Xilinx recommends that the FPGA design be modified such that the outputs in the design can be 3-stated. The system should drive the 3-state control signal in order to 3-state the I/Os during configuration. Also see (Xilinx Answer 18278) for more information on the importance of 3-stating your outputs just before and upon initiating a reconfiguration.
The output is based on the configuration of the IOB which will be design dependent. Different components instantiated in the IOB will have a different behavior on the output of the IOB.
The output of the IOB is based on the configuration of this cell, but for a given cell and configuration all devices will behave the same. So, if an IOB drives high before DONE goes high, this will occur on all devices and will not be an intermittent occurrence.
The IOB becomes active after the device has been configured and GHIGH is released, and will be active until GTS is released. GHIGH is released after the CRC check at the end of the data load portion of the bit file, and there are further details in the configuration user guide.
The IOB can drive actively high, but can also just enable the pullup internal to the IOB. External pulldowns on the part might work, depending on the design and configuration of the IOB.
NOTE: This issue does not apply to Spartan-3 and later Spartan devices, or to Virtex-4 and later devices.
1. Insert OBUFEs on the outputs that are transitioning during configuration.
2. Bring the 3-state control signal of the OBUFE to an external I/O pin.
3. On the board, connect the 3-state control I/O pin to the DONE pin. The DONE pin drives the control signal Low, and 3-states the outputs.