AR# 18278


Virtex-II/-II Pro - I/O outputs glitch during reconfiguration


During reconfiguration of a Virtex-II device, a given output might glitch soon after PROG is pulsed low. Note that this occurs only during reconfiguration (not initial configuration) and when the output was previously configured with a FAST slew rate. This behavior has been observed with LVTTL and LVCMOS33 I/O standards, and most likely occurs with other I/O standards as well. The magnitude of the glitch seems at least partially dependent on the previously programmed drive strength of the output, and has been observed to be as high as 2V.

The glitch seems to coincide with the DONE and INIT pins transitioning Low soon after PROG is pulsed Low. The glitch has only been observed in Serial and SelectMAP configuration modes. It is not evident when reconfiguring through JTAG. However, an output can transition High and stay High through all of configuration when reconfiguring through JTAG. See (Xilinx Answer 18277) for more information.


Xilinx strongly recommends designing systems in such a way that outputs from the device can be ignored during configuration. If the system cannot ignore glitches on outputs during configuration, Xilinx recommends that the FPGA design be modified such that the outputs in the design can be 3-stated. The system should drive the 3-state control signal in order to 3-state the I/Os just before and upon initiating a reconfiguration. See (Xilinx Answer 18277) for more information on why 3-stating your outputs during configuration can also be important.

NOTE: This issue does not apply to Spartan-3 and later Spartan devices, or to Virtex-4 and later devices.

Design Example

Insert OBUFEs on the outputs that are transitioning during configuration. Bring the 3-state control signal of the OBUFE to an external I/O pin. Ensure that the system drives this pin Low prior to pulsing the PROG pin Low.

AR# 18278
Date 12/15/2012
Status Active
Type General Article
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