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AR# 18316

LogiCORE SPI-4.2 (POS-PHY L4) v6.0.1- RDClk_P pinout of VP30 (East side) generated by Core Generator is different than SPW's

Description

General Description

When using SPI-4.2 core for 2VP30 with I/O on Bank 2 & 3 (East Side), you might receive following error when running MAP:

"ERROR:Pack:679 - Unable to obey design constraints (LOC=D18) which require the

combination of the following symbols into a single DIFFM component:

DIFFAMP symbol

"pl4_snk_top0/pl4_snk_clk0/DynamicAlignV2.rdclk_ibufg0/IBUFGDS" (Output

Signal = pl4_snk_top0/pl4_snk_clk0/rdclk_int)

PAD symbol "RDClk_P" (Pad Signal = RDClk_P)

SlaveBuffer symbol "RDClk_P.DIFFIN" (Output Signal = RDClk_P.DIFFIN)

PAD symbol "RDClk_East_P" (Pad Signal = RDClk_East_P)

More than one pad symbol. Please correct the design constraints accordingly."

This is because the location constraint for RDClk_P in the UCF file of VP30 (East side) generated by COREGen is different than in the pinout available from SPW (Xilinx Sales Partner Web). SPW is accessible by Xilinx FAE.

UCF by Core Generator: RDClk_P LOC = "D18"

Pinout from SPW: RDClk_P LOC = "H18" or Alternative "J17"

Solution

Either of the pin locations mentioned above (UCF or SPW) will work. However, you might run into following issues:

If you have build the board with the pinout from SPW, and if you use the UCF generated by the Core Generator, your design will not work as the board and the design will have different placements. In this case, Xilinx suggests that you change the UCF file to match the SPW's pinout. Use RDClk_P=H18 and RDClk_N= J18 or, alternatively, RDClk_P=J17 and RDClk_N= H17. NOTE: You will need to modify the location constraints for the corresponding BUFGMUXs in the UCF file as indicated below.

If you are implementing the two SPI-4.2 cores in a single FPGA, you will get a placement conflict error. The core with I/O placement on Bank 2 & 3 is known as East core, and I/O placement on Bank 6 & 7 as West core. The East and the West core has RDClk_P locked to the same location "D18", therefore, causing the placement error. In this case, Xilinx also suggests that you change the UCF file of the East core to match the SPW's pinout. NOTE: You will need to modify the location constraints for corresponding BUFGMUXs in the UCF file as indicated below.

Correct Placement of BUFGMUX

For RDClk_P = D18 and RDClk_N = H17:

# Select global clock buffer associated with RDClk_P/N input pair

INST "pl4_snk_top0/pl4_snk_clk0/DynamicAlignV2.rdclk0_bufg0" LOC = BUFGMUX6S;

INST "pl4_snk_top0/pl4_snk_clk0/DynamicAlignV2.rdclk180_bufg0" LOC = BUFGMUX7P;

For RDClk_P = H18 and RDClk_N = J18:

# Select global clock buffer associated with RDClk_P/N input pair

INST "pl4_snk_top0/pl4_snk_clk0/DynamicAlignV2.rdclk0_bufg0" LOC = BUFGMUX4S;

INST "pl4_snk_top0/pl4_snk_clk0/DynamicAlignV2.rdclk180_bufg0" LOC = BUFGMUX5P;

For RDClk_P = J17 and RDClk_N = H17:

# Select global clock buffer associated with RDClk_P/N input pair

INST "pl4_snk_top0/pl4_snk_clk0/DynamicAlignV2.rdclk0_bufg0" LOC = BUFGMUX2S;

INST "pl4_snk_top0/pl4_snk_clk0/DynamicAlignV2.rdclk180_bufg0" LOC = BUFGMUX3P;

Furthermore, if you are implementing both East and West side cores into single FPGA, you will also need to modify the placement of SysClk and all the BUFGMUX and DCM for either the East or the West core.

AR# 18316
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article