We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 18325

6.1 EDK, SimGen - Sub-module simulation is not supported


Keywords: SimGen, simgen, sub-module, simulation, EDK, edk

Urgency: Standard

General Description:
When simulating my sub-module design, SimGen errors out, stating that sub-module simulation is not supported.


To work around this problem, you can change the Design Hierarchy to toplevel design.

Currently, Behavioral simulation for Verilog is not supported. See (Xilinx Answer 15796).
AR# 18325
Date 04/09/2007
Status Archive
Type General Article
Page Bookmarked