AR# 18333


Project Navigator - Instantiated components are marked with a question mark (?) in the Project Navigator Sources in the Project window


In the Project Navigator Sources in the Project window, all of the source files added to a project are represented on a hierarchical tree as they are used in a design. What does it mean if an instantiated component has a question mark icon next to it in the hierarchy?


A question mark next to a component name in the hierarchy indicates that (1) a component has been instantiated in the source file immediately above it in the hierarchy, and (2) Project Navigator does not recognize the component name as a source added to the project.

This can happen in the following situations:

1. The underlying source has not yet been added to the project.

2. The underlying source has been added to the project, but the module name does not match the component instantiation name.
- Verify that the module name(s) in the lower-level source file match the component name in the higher-level source file.

3. Black Box instantiations in VHDL.
- In Project Navigator 6.1i and later, instantiated black box components are shown with a question mark to show that they are included in the design. This is a change from the 5.2i behavior where components with a black box attribute did not show up in the source hierarchy. In this case, the design should still be able to synthesize and implement without error, as long as there is a netlist associated with the black box in the project directory or search path. The question mark icon can be changed to a module file icon by creating a new file with an entity and an empty architecture for each black box component.

4. Instantiated Xilinx primitives (UniSim components) are recognized by Project Navigator's hierarchy parser and should not be displayed in the hierarchy. However, in ISE 8.1i instantiated primitives will be displayed in the hierarchy if the UniSim library is not included with a "use" or "include" statement.

5. Thecomponent has not been generated yet. Inthe simulation view (Post Translate, Post-MAP and Post-PAR)the UUT is generated from a Xilinx netlist format (e.g. NGC, NCD) file. The components will not be shown in the hierarchy until after the "Generate Simulation Model" process corresponding to the selected implementation stage has been run.

6. A Simulation only Test Bench file is added to a project asassociated with the"Implementation" or "All" view. This effectively tells Project Navigator that a simulation model needs to be generated for this module. To correct this do the following:
A.Go to "File" tab in the "Design" window,
B.Right click on module in question and select "Source Properties",
C.Change the "View Association" to "Simulation".

AR# 18333
Date 12/15/2012
Status Active
Type General Article
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