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AR# 18350

6.1i XST - Attributes on VHDL/schematic components incorrectly override attributes placed on instances

Description

Keywords: XST, attribute, VHDL, order, precedence, instance, instantiation, component, schematic, sch2vhdl, schematic, ignore, default

Urgency: Standard

General Description:
An attribute value on an instance should override the value of the same attribute placed on the component declaration. However, in the 6.xi software, XST is passing the attribute value on the component instead of the instance.

What is the attribute passing order precedence in VHDL?

Solution

1

When passing attributes to components and instances, the compiler adds any attribute passed to the component first. Then, the compiler adds any attribute that is passed to instances. If the same attribute is passed to an instance and to a component, the attribute value passed to the instance overrides the attribute passed to the component, as in the following example:

:
:
component CLKDLL
port ( CLKFB : in std_logic;
CLKIN : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK90 : out std_logic;
CLKDV : out std_logic;
LOCKED : out std_logic);
end component;

attribute CLKDV_DIVIDE : STRING ;
attribute CLKDV_DIVIDE of CLKDLL : COMPONENT is "2.000000"; -- attribute on component
attribute CLKDV_DIVIDE of CLKDLL_INSTANCE : LABEL is "8.000000"; -- attribute on instance
:
:

The attribute on CLKDLL_INSTANCE should override the attribute on CLKDLL. However, XST does not adhere to the precedence rules and passes the attribute on the component regardless. You can work around this issue by removing the attribute on the component.

If you use ECS, you must either modify the ".vhf" file produced by ECS or pass the constraint through a UCF.

This problem has been fixed in the latest 6.2i Service Pack available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 6.2i Service Pack 3.

2

Another possible solution for ECS schematic users is to select a simulation environment of Verilog instead of VHDL:

1. Highlight the FPGA device in the "Sources in Project window".
2. Right-click and select "Properties...".
3. Change "Generated Simulation Language" from VHDL to Verilog.

This problem has been fixed in the latest 6.2i Service Pack available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 6.2i Service Pack 3.
AR# 18350
Date Created 11/04/2003
Last Updated 03/07/2006
Status Archive
Type General Article