We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 18361

XST - "ERROR:HDLCompilers:27 - <file>.v line xx Illegal redeclaration of '<name>'"


Keywords: Verilog, synthesize

When synthesizing a Verilog design with XST, the following error might occur:

"ERROR:HDLCompilers:27 - <file>.v line xx Illegal redeclaration of '<name>'"


Examine your Verilog code prior to the line number listed in the error to see where the name listed has been declared. The name might have been used in a different manner (as a module name, parameter, task, function, etc.) or referenced in a different file (accessed by an "include statement," for example).

To avoid this error, remove the redundant declaration or change the name of one of the instances.
AR# 18361
Date 01/22/2006
Status Active
Type General Article
Page Bookmarked