AR# 18415: 7.1i XST - "ERROR:HDLParsers:856 No default value for unconnected port <C>"
7.1i XST - "ERROR:HDLParsers:856 No default value for unconnected port <C>"
Keywords: ECS, schematic, VHDL
General Description: When I synthesize a design (often from a schematic created in ECS), the following error occurs:
"ERROR:HDLParsers:856 - <file>.vhf Line xx. No default value for unconnected port <C>."
This error occurs when a Xilinx library primitive is placed in a design (via schematic or HDL instantiation) and pins are left unconnected or "open". For example, if an FDCE is placed in an ECS schematic and the clock pin is left unconnected, this instantiation is written to the .vhf file (if VHDL netlisting is selected):
XLXI_1 : FDCE port map (C=>open, CE=>XLXN_2, CLR=>XLXN_3, D=>XLXN_4, Q=>XLXN_5);
The "open" keyword on the C port causes the error. To avoid the error, remove the open keyword because it can only be used for unconnected output ports and for unconnected input ports if the input ports have a default value. Undriven nets connected to unnecessary primitive input pins are acceptable because they are trimmed by XST; however, it is important to watch the messages from XST. Undriven signals are driven by 0, and that might be inappropriate for some situations (such as an undriven clock enable).