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AR# 18437

6.1i XST - Error in the XST User Guide on inferring Dual-Port RAM with Enable on Each Port

Description

Keywords: software, manual, RAM, dual, port, enable, 6.1, ISE, XST

Urgency: Standard

General Description : The software manual 6.1is wrong, regarding the Dual port ram with Enable on each port (inferring). The description doesn't match the VHDL/VERILOG code provided with.
http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/xst/xst0026_5.html.

Solution

1

To infer a Dual-Port RAM with enable on each port with XST, the following VHDL has to be synthesised:

VHDL
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity raminfr is
port (
clk : in std_logic;
ena, enb : in std_logic;
wea : in std_logic;
addra : in std_logic_vector(4 downto 0);
addrb : in std_logic_vector(4 downto 0);
dia : in std_logic_vector(3 downto 0);
doa : out std_logic_vector(3 downto 0);
dob : out std_logic_vector(3 downto 0)
);
end raminfr;

architecture syn of raminfr is

type ram_type is array (31 downto 0) of std_logic_vector (3 downto 0);
signal RAM : ram_type;
signal read_addra : std_logic_vector(4 downto 0);
signal read_addrb : std_logic_vector(4 downto 0);

begin

process (clk) begin
if (clk'event and clk = '1') then
if (ena = '1') then
if (wea = '1') then
RAM(conv_integer(addra)) <= dia;
end if;

read_addra <= addra;
end if;
end if;
end process;

process (clk) begin
if (clk'event and clk = '1') then
if (enb = '1') then
read_addrb <= addrb;
end if;
end if;
end process;

doa <= RAM(conv_integer(read_addra));
dob <= RAM(conv_integer(read_addrb));

end syn;

2

To infer a Dual-Port RAM with enable on each port with XST, the following Verilog has to be synthesised:


Verilog
module raminfr (clk, ena, enb, wea, addra, addrb, dia, doa, dob);

input clk, ena, enb, wea;
input [4:0] addra, addrb;
input [3:0] dia;
output [3:0] doa, dob;

reg [3:0] ram [31:0];
reg [4:0] read_addra, read_addrb;

always @(posedge clk) begin
if (ena) begin
if (wea) begin
ram[addra] <= dia;
end
read_addra <= addra;
end
end


always @(posedge clk) begin
if (enb) begin
read_addrb <= addrb;
end
end

assign doa = ram[read_addra];
assign dob = ram[read_addrb];

endmodule
AR# 18437
Date Created 11/17/2003
Last Updated 03/07/2006
Status Archive
Type General Article