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AR# 18441

EDK G13.2 - ppc405_v2_00_b mpd file incorrectly sets HDL=both

Description

Keywords: ppc405, Verilog, HDL, both

Urgency: Standard

General Description:
There is no Verilog HDL file for the "ppc405 v2_00_b", although the "HDL=both" tag is set. This causes problems using the Verilog flow.

Solution

Change line 17 in "$EDK$\hw\XilinxProcessorIPLib\pcores\ppc405_v2_00_b\data\ppc405_v2_1_0.mpd"

... from this:

OPTION HDL = BOTH

... to this:

OPTION HDL = VHDL
AR# 18441
Date Created 11/17/2003
Last Updated 04/25/2007
Status Archive
Type General Article