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AR# 18484

6.1i EDK - Structural simulation does not work for EDK cores that use BBD files

Description

Keywords: EDK, XPS, BBD, SimGen, netlists, EDN, EDIF, NGC, structural

Urgency: Hot

General Description:
Structural simulation is not supported for the following peripherals:

opb2plb_bridge_v1_00_a
opb2plb_bridge_v1_00_b
opb_atmc_v1_00_b
opb_atmc_v2_00_a
opb_ddr_v1_00_b
opb_ethernetlite_v1_00_a
opb_ethernet_v1_00_j
opb_ethernet_v1_00_k
opb_ethernet_v1_00_l
opb_ethernet_v1_00_m
opb_hdlc_v1_00_b
opb_pci_v1_00_b
plb_atmc_v1_00_a
plb_ddr_v1_00_b
plb_ethernet_v1_00_a
plb_gemac_v1_00_a
plb_gemac_v1_00_b
plb_rapidio_lvds_v1_00_a
opb_hdlc_v2_00_a
plb_ddr_v1_00_c

Each of these peripherals is dependent upon an EDIF or EDN netlist. These netlists are not automatically converted to the appropriate simulation model.

Solution

This issue has been resolved in EDK 6.2.

EDK 6.1 Resolution

You can also include a structural simulation by performing the following steps:

1. Copy the appropriate netlist(s) from the following "<EDK_Project>\implementation" directory to a temporary directory:

%EDK%\hw\XilinxProcessorIPLib\pcores\<core_name>\netlist

NOTE: Netlists without a wrapper file need a simulation model.

2. Create a new ISE project using the EDIF Flow in the temporary directory.
3. In ISE, double-click "Generate Post-Translate Simulation Mode" under "Implement Design\Translate".
4. Copy the generated VHDL or Verilog files to the "<EDK_Project>\simulation\structural" directory.
5. Open and modify the "system.do" file to include the new VHDL or Verilog file.
AR# 18484
Date Created 11/24/2003
Last Updated 03/07/2006
Status Archive
Type General Article