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AR# 18529

LogiCORE PCI Express - Can the MGT transmit and receive lane polarity be reversed or inverted?


The RocketIO blocks allow users to reverse the transmit and receive polarity by setting the TXPOLARITY and RXPOLARITY inputs. See the "RocketIO Transceiver User Guide" v2.5 (UG024) at:

Go to FPGA Device Families -> Virtex-II Pro -> RocketIO Transceiver User Guide

Is it possible to reverse the polarity of the RocketIOs when using the PCI Express LogiCORE?


Transmit Path

For the transmit path, you do not have direct access to the TXPOLARITY input on the RocketIO. This bit is tied Low inside the PCI Express Core allowing normal polarity on the RocketIO transmitter. However, if you want to reverse the polarity, you can do so by using FPGA Editor to edit the routed NCD file; open the RocketIO block in FPGA editor and edit the design to drive the TXPOLARITY port on the MGT. Since the PCI Express specification has a built-in mechanism for dealing with lanes that have incorrect polarity, this port is not made available to the user. The burden to reverse the lane polarity is on the receiving side of the link, not the transmitter. So, if each link partner is compliant to the specification, there should be no need to reverse the polarity on the transmitter. Refer to section of the PCI Express Specification for more information on this subject.

CAUTION: If the x4 lane core is being used, it is important that the polarity be reversed on all 4 lanes. Otherwise, the core will not train properly with the other PCI Express device it is connected to.

Receive Path

For the receive path, the core already has a mechanism built in that recognizes if the training sets being received are inverted. If the training sets appear to be inverted, the receive path polarity will be reversed by the core. This is a requirement of the PCI Base Specification in section No modifications are required on the Receive Path in FPGA Editor to invert the lane polarity.

NOTE: This is not the same as lane reversal, which is optional and is defined in section of the PCI Base Specification v1.1. The Xilinx PCI Express Core does not support this optional behavior.

AR# 18529
Date 02/04/2013
Status Active
Type General Article