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AR# 18555

6.1i Speedfiles - "WARNING:Timing: 2719 The clock CLKCPU has a low pulse width of 1650 ps"

Description

General Description:

When performing static timing analysis on a PPC405 design, I receive the following error:

"WARNING:Timing:2719 - The clock CLKCPU has a low pulse width of 1650 ps and a

high pulse width of 1650 ps. This violates the pulse width of component

top_cpu/PPC405 which has a minimum low pulse width of 1724 ps and a minimum

high pulse width of 1724 ps.

WARNING:Timing:2719 - The clock CLKCPU has a low pulse width of 1650 ps and a

high pulse width of 1650 ps. This violates the pulse width of component

top_cpu/PPC405 which has a minimum low pulse width of 1724 ps and a minimum

high pulse width of 1724 ps."

What does this warning mean, and how do I resolve it?

Solution

A "clock-pulse-width check" checks to make sure that a component is clocked within its frequency boundaries. In this case, the PERIOD constraint is checked against a minimum pulse width value in the speedfile. This check will make sure that duty cycle restrictions are met for the component. NOTE: The timing also performs a frequency check.

Various settings on the PPC405 instance can change which pulse value is used.

If operand forwarding is enabled by the user (the default is disabled), a bug exists where a tighter check will be performed. If operand forwarding is disabled, there is a 50-50 duty cycle on the clock, and the following frequency warning does not accompany it, these warnings can be safely ignored.

"WARNING:Timing:2751 - The clock ppc_clk_s has a period (frequency) specification

of 3333 ps (300.03 Mhz). This violates the minimum period (maximum

frequency) for component ppc405_0/ppc405_0/PPC405_i of 3449 ps (289.94 Mhz)."

This is supposed to be fixed in the next release of the software.

AR# 18555
Date Created 09/03/2007
Last Updated 01/18/2010
Status Archive
Type General Article