UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 18572

LogiCORE 10 Gigabit Ethernet MAC v4.0 - Release Notes

Description

General Description: 

This Answer Record contains the Release Notes for the 10 Gigabit Ethernet MAC v4.0 core.

Solution

10 Gigabit Ethernet MAC v4.0 

 

Software Requirements 

 

ISE 6.1i with Service Pack 3 and IP Update #1 or newer 

 

New Features in v4.0 

- Added support for ISE 6.1i software. 

- Added capability to select no physical interface to allow the PHY-side interface of the core to be connected to user logic within the FPGA, rather than restricting the interface to an external XGMII or XAUI interface. 

- Added capability to support transmission-only or reception-only cores. 

- XAUI configuration no longer requires an STA entity to be elsewhere in the system to manage the XAUI block when there is no host interface present. 

- Updated the ENMCOMMAALIGN and ENPCOMMAALIGN logic to use specific slices (rather than a range) for the logic, as recommended in the RocketIO User Guide. 

 

Bug Fixes in v4.0 

- Fixed an issue in which outbound frames were corrupted when near-maximum length frames and near-minimum length IPG's were transmitted. 

- Added additional constraints to cover unconstrained paths in the DDR logic of the XGMII interface. 

- Corrected an issue in which the receiver fails to recover in time, following a runt/error frame, to accept the new frame when the IFG is a single column of idles. 

- Fixed an issue in which the upper 32 bits of the statistic counters incorrectly incremented. 

 

Known Issues 

10 Gigabit Ethernet MAC v4.0 core cannot be generated in Linux.  

- This was fixed in 6.2i. To work around the issue, generate the core in Solaris or on a PC and then implement the design on Linux. 

 

The 10 Gigabit Ethernet MAC v4.0 core cannot be generated with a Component Name of "xgmac_core" in COREGen; doing so causes synthesis to fail in XST.  

- Refer to (Xilinx Answer 18747) for more information. 

 

In the 10 Gigabit Ethernet MAC v4.0 core, the MDIO interface of the XAUI block does not work properly. 

- To work around this issue, please install the patch below and regenerate the core. For more information, please see (Xilinx Answer 19393)

 

Patch 

To resolve the issues listed in (Xilinx Answer 19393), apply the following patch to the 6.1.03i IP Update #1 or 6.2i (any service pack) installation: 

 

http://www.xilinx.com/txpatches/pub/swhelp/coregen/xgmac_v4_0_patch_03may04.zip
http://www.xilinx.com/txpatches/pub/swhelp/coregen/xgmac_v4_0_patch_03may04.tar.gz
 

Install the patch as follows: 

1. Unzip the contents of the ".zip" file or "tar.gz" archive to the root directory of the Xilinx installation. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure pre-defined in the archive.  

 

PC 

Determine the Xilinx installation directory by typing the following at the command prompt: 

"echo %XILINX%" 

 

UNIX or Linux 

Determine the Xilinx installation directory by typing the following: 

"echo $XILINX" 

 

NOTE: You might need to have system administrator privileges to install the patch.  

 

2. After installing the patch, regenerate the Gigabit Ethernet MAC core from the CORE Generator. The core produced will contain the fix.

AR# 18572
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article