After installing the ISE 6.1i Service Pack 3 (6.1.03i), my design no longer meets setup timings on my I/Os. Why?
This is due to a change in the default setting of the DESKEW_ADJUST DCM attribute. The DESKEW_ADJUST setting can be set to SYSTEM_SYNCHRONOUS (default), SOURCE_SYNCHRONOUS, or an integer from "0" to "15". In ISE 6.1i, the SYSTEM_SYNCHRONOUS(default) setting for all Virtex-II Pro devices is equal to setting DESKEW_ADJUST to "5". This setting is incorrect; the default should be "6" or "7" depending on the device size. This default setting is used to ensure that the device has "0" or negative hold times.
This setting only affects a design if the DCM is configured in one of the following scenarios:
- When CLKIN is driven by IBUFG and CLKFB is an internal feedback via BUFG.
- When CLKIN is driven by a BUFG and CLKFB is driven by IBUFG.
The following table shows how the default setting has changed with the history of the tools.
NOTE: For more information on DCM attributes, please refer to the Virtex-II Pro User Guide at:
-> Virtex-II Pro Platform FPGA User Guide -> Design Considerations -> Digital Clock Managers (DCMs) -> Summary of All DCM Attributes
If your design no longer meets static timing analysis, Xilinx recommends changing the applicable DCM DESKEW_ADJUST setting to "5". However, if you change the setting, you should check that you do not have positive hold times.
Currently, this change must be applied to the HDL code or to the UCF. Your design must be re-implemented (mapped, placed-and-routed) for the change to take effect.