We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 18634

PROM XC18V00 - A PROM data failure causes an FPGA configuration failure (DONE stays Low and INIT stays High)


General Description:

XC18V00 devices with the topmark "ART" are sensitive to noise on the CE# and OE/RESET# pins during PROM power-up. If a slow ramping or noisy signal is present on the CE# or OE/RESET# pin during power-up, the internal address counter may be corrupted, which causes misalignment of the PROM data. The failure symptoms are an incorrect SYNC word or preamble. This misalignment will prevent the FPGA from properly configuring. The FPGA's DONE pin remains Low, and the FPGA's INIT pin remains High.

This Answer Record is provided to document the sensitivity of the XC18V00 with the "ART" top mark to slow ramping or noisy signals on CE# and OE/RESET#.

For general guidelines on FPGA configuration failure, please see Configuration Problem Solver:



You can correct this problem by providing clean, quick ramping signals on both CE# and OE/RESET# during power-up.

1. Ensure that an external resistor of 4.7Kohm (or lower) is connected to the PROM's OE/RESET# pin (the FPGA's INIT pin).

2. When you use the FPGA's DONE pin to drive the PROM's CE# (to reduce standby power), make sure that the CE# signal is within specification and has a fast rise and fall time. Use an external buffer to drive any LED "DONE" indicators.

Using the DONE pin to directly drive (un-buffered) both the LED and the PROM CE# pin will typically exceed the standard 12mA max sink current on the FPGA DONE pin; this causes a slow-ramping CE# signal. If the PROM low-power standby mode is not required, the CE# connection to the DONE pin is not required, and the CE# pin can be tied to Ground.

(NOTE: When CE# is not connected to DONE, the FPGA DONE pin must still be pulled up to VCCO to allow the FPGA configuration start-up sequence to complete.)

3. Use the Master mode FPGA CCLK pin as the configuration CLK source instead of using an external free running clock.

Please see the "Customer Advisory: Intermittent Synch Word - XC18V00" at

and the "XC18V00 PROM Errata and Deviations from XC18V00 Data Sheet" at


AR# 18634
Date 12/15/2012
Status Active
Type General Article