AR# 18645

6.3 System Generator for DSP - Why do I get simulation mismatches at the output of the FFTx when VOUT is Low?

Description

Keywords: SysGen, MATLAB, Simulink, 6.3, 7.1

Why do I get simulation mismatches at the output of the FFTx when VOUT is Low?

Solution

The behavioral simulation mismatch is a side effect of different behaviors between Radix 4 Streaming I/O, Radix 4 Burst I/O and Radix 2 Minimum Resources architectures of the FFT. The Radix 4 Burst I/O and Radix 2 Minimum Resources architectures maintain the last valid output value on the real and imaginary signals whenever the VOUT signal goes Low.

The Radix 4 Streaming I/O architecture does not do this check; instead, the address generator in the Radix 4 Streaming I/O architecture just outputs random values at the output. This problem is avoided by placing a register on the output of the FFTx and using the VOUT as an enable for the registered outputs.

Also, since the Radix 4 Streaming I/O will be obsolete in future versions of the FFTx, it is highly recommended that you move the Pipelined Streaming I/O architecture.

This is resolved in System Generator for DSP 7.1.
AR# 18645
Date 01/12/2006
Status Archive
Type General Article