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AR# 18668

7.1i Timing Analyzer/TRCE - Timing tools do not properly adjust for my equivalent positive phase shift

Description


General Description:

I am trying to perform a negative phase shift on my DCM, but I cannot get the tools to analyze my OFFSET/IN constraints correctly. I looked at (Xilinx Answer 13349), and put a positive phase shift on the DCM that is equivalent to my required negative phase shift. However, this solution caused TRCE to report a hold violation on my OFFSET/IN constraint.



What can I do to make the tools handle this correctly? Do I have to adjust all of my OFFSET/IN values to account for this (which would be a false external relationship)?

Solution


This Answer Record describes two ways to solve this issue. Both methods are valid, but the second one is probably cleaner.



Method 1

1. Constrain your design with an OFFSET/IN BEFORE and define the relationship to the clock as you normally would.

2. If your data is going to arrive at the pins of the FPGA 3 ns before the clock, then make your OFFSET/IN BEFORE equal to 3 ns.

3. Put a negative phase shift on the DCM for timing analysis. The negative phase shift will be accounted for correctly in the Static Timing Analysis.

4. Before creating the bit file, change the phase shift on the DCM to the equivalent positive phase shift but do not perform timing analysis again.



Method 2

1. Constrain your design with an OFFSET:IN AFTER and put a positive phase shift on the DCM that is equivalent to the negative phase shift that you want. As a result, you can perform Timing Analysis with your final NCD file. The reason for this is because of the way the OFFSET constraint works:

- If you define your OFFSET/IN with the keyword BEFORE, then the data has setup/hold checks with respect to the clock that arrives after the data.

- If you define your OFFSET/IN with the keyword AFTER, then the data has setup/hold checks with respect to the clock that arrives before the data.

2. If you are doing an equivalent positive phase shift to work around a negative phase shift, then you will want to define your data with respect to the previous clock edge (OFFSET/IN AFTER).
AR# 18668
Date Created 09/03/2007
Last Updated 09/16/2011
Status Archive
Type General Article