AR# 18692


CPLD CoolRunner XPLA3 - Similar logic paths have different delays (universal control term - UCT)


Urgency : Standard 


General Description: 

A design contains several identical clock to out paths (using different clock signals). Some of the paths have different timing values than the other. Why is that the case?


CoolRunner XPLA3 CPLDs have an architectural feature called the Universal Control Term (UCT). This allows internally generated signals to utilize dedicated resources that route to all function blocks. For more information, see (Xilinx XAPP334) "Utilizing XPLA3 Universal Control Terms." 


Some of the paths are utilizing the UTCs, and others are not. This is because of the different timing figures. There is no way to specify which signals are to use the UTCs. You may disable the usage of UTCs by deselecting the option Use Function Block Shared PTerm Clocks.  


If you are using a command line interface, the switch is "-nouctclkopt".

AR# 18692
Date 05/08/2014
Status Archive
Type General Article
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