When targeting a GT10 design in Verilog and using Synplify for synthesis, I receive the following error in NGDBuild:
"ERROR:NgdBuild:710 - GT10_CUSTOM symbol instance 'GT10_CUSTOM_INST' could not be resolved due to invalid pin 'PMAREGADDR(5)'."
Why is this?
Synplify is writing out the ports incorrectly. The module declaration for the GT10 in the "unisim.v" is incorrect, and this is why the ports do not match.
The error message is misleading; it should say RXCHECKINGCRC not a valid pin.
This problem can be worked around by using XST for synthesis.
Another way to work around this problem is:
1. Find the "unsim.v" file in "C:\Program Files\synplicity\Synplify_734\lib\xilinx".
2. Open this file in a text editor.
3. Seek the specific GT10 component.
4. Replace the module declaration of the GT10 component in the "unisim.v" file with the one that is available in the "unisims" directory provided by Xilinx:
5. Re-run synthesis in Synplify and add this modified "unisim.v" file.