We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 18791

Virtex-II/Pro, DCM - What is the input duty cycle requirement when using CLKIN_DIVIDE_BY_2 attribute?


Is there a duty cycle requirement for the input clock when using the CLKIN_DIVIDE_BY_2 attribute?


Yes, there is a duty cycle requirement for the input clock.

When you use the CLKIN_DIVIDE_BY_2 attribute with the DCM, the duty cycle requirement depends on the input clock frequency.

Frequency Less than 400 MHz

For Virtex-II and Virtex-II Pro:

Use the Input Clock Low/High Pulse Width numbers.

For Virtex-4 and Virtex-5:

Use the Input Clock Duty Cycle Tolerance numbers.

These numbers are specified in the DC and Switching Characteristics section of the data sheet for the device family.


Frequency greater than 400 MHz

The duty cycle should be 45/55 to 55/45.

AR# 18791
Date 12/15/2012
Status Active
Type General Article