We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 18800

6.2i, iMPACT - Virtex-II Serial or SelectMAP configuration using an encrypted bit stream fails, but DONE always goes High with JTAG whether the correct key is loaded or not


General Description: 

Using iMPACT 6.2i, the Virtex-II/Pro FPGA is programmed successfully via JTAG with an encrypted bit stream. However, when I attempt Serial or SelectMAP configuration, programming fails and DONE does not go High. Programming the FPGA in any configuration mode with an un-encrypted bit stream is always successful.


When creating an encrypted bit file, check to make sure the correct startup clock is selected when the bit stream is generated. 


-- To configure via JTAG, generate the bit stream with the startup clock set to JTAG clock.  

-- To configure via Serial or SelectMAP, generate the bit stream with the startup clock set to CCLK. 

-- Ensure the correct key has been loaded into the FPGA.  


When not using encryption, iMPACT can automatically modify the startup clock setting in the bit stream to use either the JTAG clock or the CCLK as the startup clock depending on the selected configuration mode. If the user generated the bit stream with the startup clock set to JTAG clock but wants to configure via Master Serial, the iMPACT tool is "smart" enough to decipher the non-encrypted bit stream and alert the user that it will be changing the startup clock from JTAG clock to CCLK. However, with an encrypted bit stream, it is impossible for the iMPACT tool to determine or modify the startup clock option set within the encrypted bit stream. Therefore, it is up to the user to make sure to select the appropriate startup clock when the bit stream is first generated.  


To change the startup clock in the Project Navigator, select and right-click the "Generate Programming File" function in the Processes for Source window and go to the Startup Options tab. To change the startup clock via command line, use the bitgen -g StartupClk option.  


If the FPGA is loaded with incorrect key or no key, it is still possible for DONE to go High if the part is configured with encrypted bit stream through JTAG. However, this might result in the internal routing contention due to the incorrect bit stream and damage the part.

AR# 18800
Date 05/16/2014
Status Archive
Type General Article
Page Bookmarked