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AR# 18842

8.1i CPLD TSIM - CPLD Timing simulation does not show I/O termination (Bus hold/Keeper and Pull up)

Description

Urgency: Low  

 

General Description : 

Timing simulation shows a 3-stated output as 'Z' instead of 'H' as it should, indicating a weak pull-up.

Solution

A work-around to emulate a pullup is to manually add the pullup component to the necessary I/O pins in the back-annotated timing file. No work-around exists to emulate the bus-hold "keeper" circuitry. 

 

VHDL 

 

You will need to edit the "DESIGNNAME_timesim.vhd" file. Attach a copy of the following component to each I/O signal that requires a pullup. 

 

PU1_1 is an instance name, and needs to be different for each pullup component. IOSIGNAL is the name of the I/O pin. 

 

PU1_1 : X_PU 

port map (  

O => IOSIGNAL  

);  

 

Verilog 

 

You will need to edit the "DESIGNNAME_timesim.v" file. Attach a copy of following component to each I/O signal that requires a pullup. 

 

PU1_1 is an instance name, and needs to be different for each pullup component. IOSIGNAL is the name of the I/O pin. 

 

X_PU PU1_1 ( 

.O(IOSIGNAL) 

);

AR# 18842
Date Created 09/03/2007
Last Updated 05/08/2014
Status Archive
Type General Article