When running PlatGen on a design containing the PLB GEmac core wired to both the Master and Slave ports, I receive the following error:
"ERROR:MDT - plb_v34 (plb) - C:\working\Gm\system.mhs:106 - 2 SLAVE(s) allowed, but POSITION 3 assigned"
This is caused because in this design, the position of the slave and master is set to the same position value:
BUS_INTERFACE MSPLB = plb
The position value generated by PlatGen is shared between both masters and slaves, since the BUS_INTERFACE line is shared.
Although the value calculated by PlatGen is legal for masters (there are 3 masters on the plb), it is illegal for the slave (there are only 2 slaves on the plb).
To work around this issue, set the position value on the bus.
BUS_INTERFACE MSPLB = plb, POSITION = 2