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AR# 18889

8.1i Virtex-II MAP - "ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=U11_U20/hset, RLOC=R13C0.S1)"


A case has been seen where a design was mapped with unused logic trimming disabled (-u), and it failed during packing with an error indicating that there were too many LUTs being RLOC'd to a slice. Examination of the logic revealed that the logical design was correct but that some MUXCY and XORCY logic was being transformed into LUT logic apparently as a result of trimming behavior.

NOTE: This Answer is a good match for your case only if logic trimming has been disabled, and the pack error reports more than two LUTs being used with the message, "There are more than two function generators."

"ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=U11_U20/hset,

RLOC=R13C0.S1) which require the combination of the following symbols into a

single SLICE component:

LUT symbol "U11_U20/BU30" (Output Signal = U11_U20/N40)

FLOP symbol "U11_U20/BU32" (Output Signal = U11_PeriodCounterOutput<4>)

LUT symbol "U11_U20/BU34" (Output Signal = U11_U20/N93)

LUT symbol "U11_U20/BU36" (Output Signal = U11_U20/N41)

LUT symbol "U11_U20/BU28" (Output Signal = U11_U20/N88)

FLOP symbol "U11_U20/BU38" (Output Signal = U11_PeriodCounterOutput<5>)

There are more than two function generators. Please correct the design

constraints accordingly."


This problem is being investigated for a fix in a future release. Meanwhile, it can be avoided by setting the following environment variable that reverts to trimming behavior that existed before version 6.1i.

Windows PCs


Solaris and Linux


For more general information about setting ISE environment variables, see (Xilinx Answer 11630).

AR# 18889
Date 12/15/2012
Status Active
Type General Article