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AR# 18903

LogiCORE SPI-4.2 (POS-PHY L4) v6.1 - Migrating from v6.0.1 to v6.1 (Migration Guide)


General Description:  

This Answer record describes how to migrate from v6.0 to v6.1 of the SPI-4.2 core. It also describes the signal changes made to the core. While every attempt was made to keep constraints and input and output signals as consistent as possible between versions, certain modifications are required to upgrade from v6.0 to v6.1. The following sections are included in this Answer Record:  


- Core Signal Changes  

- Wrapper File Changes  

- NCF File Changes  

- UCF File Changes  

- UCF Migration Steps  


NOTE: If you are implementing Dual SPI-4.2 design (two SPI-4.2 in single FPGA), additional steps are needed following the steps mentioned in this Answer Record. Please see (Xilinx Answer 19039).


Core Signal Changes 


NOTE: The following signals were added in the v6.1 core.  


SnkBusErrStat(7:0) (Output) - new in v6.1  

Please see the data sheet for more information. If not needed, leave unconnected.  


SnkDIP2ErrRequest (Input) - new in v6.1  

Please see the data sheet for more information. If not needed, tie it to "0."  


SnkDPAModeSel (Input) - new in v6.1 

Please see the data sheet for more information. Required to tie it to "1."  


Wrapper File Changes  

The v6.1 wrapper file replaces the v6.0 wrapper file, or manually add/delete the signal changes mentioned above.  


NCF File Changes  

The v6.1 NCF files replace the v6.0 NCF files.  


UCF File Changes  

The UCF file must be updated via either Option A or Option B below:  


Option A  

Replace all SPI-4.2 constraints in the UCF file with the SPI-4.2 constraints provided in the v6.1 release (use the v6.1 UCF files instead of the v6.0 UCF files).  


Option B  

Follow the instructions below ("UCF Migration Steps") to migrate the existing PL4 UCF constraints so they are compatible with v6.1. Note that the "#" character can be substituted for numbers and "<>" are used as fillers following phrases.  


UCF Migration Steps  

There are two types of modifications necessary to migrate to SPI-4.2 v6.1: 


General Modifications: 


1. The Phase Shift of the RDClk DCM has changed to 25 for all Virtex-II devices 

INST "pl4_snk_top0/pl4_snk_clk0/LowFreq.StaticAlign_StaticAlign.rdclk_dcm0" PHASE_SHIFT = 25; 


INST "pl4_snk_top0/pl4_snk_clk0/LowFreq.StaticAlign_StaticAlign.rdclk_dcm0" PHASE_SHIFT = 40; 


2. Timespec and TNM constraints are modified to support dual core solutions. These modifications are specific to the bank 2/3 implementations and apply only to customers who are using multiple SPI-4.2 cores in a single device. (Xilinx Answer 19039) details this process. 


Device Specific Modifications: 


1. Added constraint to the following FG676 devices in bank 6/7: 2v2000fg676, 2v3000fg676, 2vp20fg676, 2vp30fg676, 2vp40fg676 

For LVTTL Status Pins: 

NET "RSClk" LOC = "Bank6";  

NET "RStat(0)" LOC = "Bank6";  

NET "RStat(1)" LOC = "Bank6";  

or for LVTTL Status Pins: 

NET "RSClk_P" LOC = "Bank6";  

NET "RStat_P(0)" LOC = "Bank6";  

NET "RStat_P(1)" LOC = "Bank6";  


2. Added Constraints to 2v6000ff1517 Static Alignment in bank 6/7 with 64-Bit Backend: 

INST "pl4_snk_top0/pl4_snk_core0/pl4_snk_wr0/worden_d3[1]" U_SET = pl4_snk_wr_d1 ; 

INST "pl4_snk_top0/G_81" U_SET = pl4_snk_wr_d1 ; 

INST "pl4_snk_top0/pl4_snk_core0/pl4_snk_wr0/worden_d3[1]" RLOC = "X0Y0" ; 

INST "pl4_snk_top0/G_81" RLOC = "X2Y0" ; 


3. Changed Source I/O Origin Constraint on 2v8000ff1517, Static Alignment in bank 6/7: 

INST "pl4_src_top0/pl4_src_io0/src_rdy.2.rdy_hi_rdy_hi.src_rdy_hi" RLOC_ORIGIN=X0Y68; 


INST "pl4_src_top0/pl4_src_io0/src_rdy.2.rdy_hi_rdy_hi.src_rdy_hi" RLOC_ORIGIN=X0Y40; 


4. Added constraint to the 2vp70ff1704 in bank 7: 

For LVTTL Status Pins: 

NET "RSClk" LOC = "AE41"; 

NET "RStat(0)" LOC = "AE35"; 

NET "RStat(1)" LOC = "AE31"; 

or for LVTTL Status Pins: 

NET "RSClk_P" LOC = "AE41"; 

NET "RStat_P(0)" LOC = "AE35"; 

NET "RStat_P(1)" LOC = "AE31";

AR# 18903
Date 05/16/2014
Status Archive
Type General Article
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