The Digital Down Converter (DDC) v1.0 indicates in CORE Generator that it does not support Virtex-4 or Spartan-3/3E. When will it support these architectures, or can the DDC generated for Virtex-II Pro be re-targeted to one of these architectures?
The FPGA fabric for the Virtex-II/-II Pro, and Virtex-4/Spartan-3/3E are similar. The fundamental difference between the Virtex-4/Spartan-3/3E and the Virtex-II/-II Pro is the CLB with two normal slices (SliceM) and two non-SRL16E/RAM16x1 (SliceL). As long as Relationally Placed Macros (RPMs) are not used, these differences do not affect using the Virtex-II Pro Core in a Virtex-4 or a Spartan-3/3E.
To use the core for Virtex-4 or Spartan-3/3E, follow these steps:
1. Change the device for your ISE project to Virtex-II Pro.
2. Select "Add a New Source" (to your ISE project) and select CORE Generator IP.
3. Run the CORE Generator GUI and generate the DDC Core.
4. Change the device for your ISE project back to Virtex-4 or Spartan-3/3E.
5. Instantiate the core in your top-level source.
6. If the core needs to be re-parameterized, repeat steps 1-4.
7. Before implementing your design, ensure that RPMs are turned off.
NOTE: The performance numbers for the area and speed will be different for Virtex-4 or Spartan-3/3E than for Virtex-II Pro implementations of the DDC Core.
For System Generator for DSP v3.1 or greater, a DDC reference design is available that can be targeted to Spartan-3/3E or Virtex-4. Enter "demos" at the MATLAB command prompt and select the "Digital down converter for GSM."