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When I run the Verilog demonstration testbench, the following message appears:
1. "# RDat Info: Stimulus Module FIFO is empty, expect idles. <simulation time>"
The following messages may also be seen:
2. "# RDat Warning: Protocol Violation #3. Idle follows non EOP control word <Simulation Time>"
3. "# TDat Error: Data Mismatch #2. Expected xxx, received xxx. <Simulation Time>"
This issue occurs when the FIFO in the Stimulus Module underflows and idles are transmitted on the RDat bus. If the idles occur on a no-credit boundary during a data burst, Message #2 will be displayed. The Data Monitor incorrectly stores the packet and compares it with the incoming
packet on TDat. This causes the Demonstration Testbench to flag an erroneous error in Message #3.
Looking at TDat, the correct core behavior is seen:
- If an idle follows immediately after an SOP control word, drop the SOP control word and send a payload resume to the previous channel.
- If an idle occurs after data (on a non-credit boundary), send a EOP abort on TDat after the data preceding the idle. Then, send a payload resume to the previous channel and continue writing data.
You can reduce the impact of this issue through the following steps:
- Set the MERGE_PAYLOAD constant to "0" in the "/test/verilog/pl4_testcase_pkg.v" file. This lengthens the time before the FIFO underflows.
- Increase the value of NumTrainSequences (re-generating the core with higher NumTrainSequences). This increases the amount of time before the Sink Core comes in frame, giving the Stimulus module time to buffer more data
- Decrease the value of DATA_NUM_TRAIN_SEQ (in the pl4_testcase_pkg.v). This increases the frequency of training on RDat, allowing the Stimulus Module to fill its FIFO.
This issue will be addressed in a future release.