We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 18945

LogiCORE SPI-4.2 (POS-PHY L4) v6.1- When I target a 2V3000 in dynamic phase alignment, PAR reports that one signal is not completely routed


General Description:

When I run tool implementations on a v6.1 SPI-4.2 core that targets a 2V3000FF1152-5 in dynamic phase alignment configuration, PAR reports that one signal is not completely routed.

When I open the design in FPGA Editor, the unrouted net is identified as GLOBAL_LOGIC0 (Ground).


To avoid this issue, rerun PAR with a different cost table entry, using the option "-t <cost table value>". Valid cost table values are between 1 and 100.

For example:

par -pl high -rl high -t 4 mapped.ncd routed.ncd

Note that if the cost table entry option is not used in the PAR command, the value defaults to "1".

AR# 18945
Date 12/15/2012
Status Active
Type General Article