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AR# 18963

6.1.1 System Generator for DSP - Why does VHDL generation fail when an output is connected to a scope?


General Description: 

Why does VHDL generation fail when an output is connected to a scope? 



A design may fail to generate when a connection to a scope within his Simulink design, but with the connection broken there is no problem generating the code. There is a Fatal error with the following details reported: 


Running s2x 


internal error: found no driver in port list 



at com.xilinx.sysgen.a.c.a(Unknown Source) 

at com.xilinx.sysgen.a.a.a(Unknown Source) 

at com.xilinx.sysgen.f.h.if(Unknown Source) 

at com.xilinx.sysgen.f.h.a(Unknown Source) 

at com.xilinx.sysgen.b.a.e.a(Unknown Source) 

at com.xilinx.sysgen.b.a.e.a(Unknown Source) 

at com.xilinx.sysgen.b.g.if(Unknown Source) 

at com.xilinx.sysgen.comp.b.do(Unknown Source) 

at com.xilinx.sysgen.comp.b.a(Unknown Source) 

at com.xilinx.sysgen.comp.GuiMain.run2(Unknown Source) 

at com.xilinx.sysgen.comp.GuiMain.main(Unknown Source) 


error in Simulink compiler


This has been fixed in System Generator 6.1.1. 



AR# 18963
Date 05/16/2014
Status Archive
Type General Article
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