When I implement an SPI4.2 v6.1 core design that targets the 2VP20FG676 device, the implementation fails in MAP, reporting the following errors:
"ERROR:Place:181 - Possibly, due to SelectIO banking constraints, the placer was unable to find a feasible solution for the IOBs in your design.
ERROR:Place:183 - The placer was not able to automatically place the IOBs in your design. Xilinx recommends that you lock your IOBs to specific pads.
ERROR:Place:412 - Failed to execute I/O Placement
ERROR:Pack:1499 - The timing-driven packing phase encountered an error."
To avoid these errors, try one of the following options:
1. If you are using ISE 6.1i, rerun the implementation using the ISE 6.2i software.
2. If you are using the "map -timing" option, run the implementation without the "-timing" option.
3. Lock down the IOBs in specific pads.