In the CORE Generator GUI, the CIC Core is not available for Virtex-II Pro, Virtex-4 and Spartan-3. Are there plans to offer this core for these devices?
The Cascaded Integrator Comb Filter LogiCORE has been replaced by the CIC Compiler. The CIC Compiler includes support Spartan-3, Virtex-4 and Virtex-5 families and should be used for all new designs.
The FPGA fabric for the Virtex-II/Virtex-II Pro, and Virtex-4/Spartan-3 are similar. The fundamental difference between the Virtex-4/Spartan-3 and the Virtex-II/Virtex-II Pro is the CLB with two normal slices (SliceM) and two non-SRL16E/RAM16x1 (SliceL). As long as Relationally Placed Macros (RPMs) are not used, these differences do not affect using the Virtex-II Core in a Virtex-4 or a Spartan-3.
To use the core for Virtex-4 or Spartan-3, follow these steps:
1. Change the device for your ISE project to Virtex-II.
2. Select "Add a new Source" (to your ISE project) and select CORE Generator IP.
3. Run the CORE Generator GUI and generate the CIC Core.
4. Change the device for your ISE project back to Spartan-3.
5. Instantiate the core in your top-level source.
6. If the core needs to be re-parameterized, repeat steps 1-4.
7. Before implementing your design, ensure that RPMs are turned off.
NOTE: The performance numbers for the area and speed will be different for Virtex-4 or Spartan-3 than for Virtex-II Pro implementations of the CIC Core.
For System Generator for DSP v6.1 or greater, a CIC reference design is available that can be targeted to Spartan-3 or Virtex-4. This design is in the Xilinx Reference Blockset under the DSP sub-menu. However, the feature set does not include programmable rate change.